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| SN54/74LS107A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOW transition of the clock. A LOW signal on CD input overrides the other inputs and makes the Q output LOW. The SN54 / 74LS107A is the same as the SN54 / 74LS73A but has corner power pins. DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY CONNECTION DIAGRAM DIP (TOP VIEW) VCC 14 CD1 13 CP1 12 K2 11 CD2 10 CP2 9 J2 8 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 14 1 J SUFFIX CERAMIC CASE 632-08 1 J1 2 Q1 3 Q1 4 K1 5 Q2 6 Q2 7 GND 14 1 N SUFFIX PLASTIC CASE 646-06 LOGIC SYMBOL 1 1 J Q 3 8 J 2 Q 5 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION 12 CP 9 CP SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC 4 K CD 13 Q 2 11 K CD 10 Q 6 VCC = PIN 14 GND = PIN 7 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 0.4 4.0 8.0 Unit V C mA mA FAST AND LS TTL DATA 5-1 SN54/74LS107A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol S bl VIH VIL VIK VOH Parameter P Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 J, K Clear Clock IIH Input HIGH Current J, K Clear Clock Input LOW Current Short Circuit Current (Note 1) Power Supply Current J, K Clear and Clock - 20 0.1 0.3 0.4 - 0.4 - 0.8 -100 6.0 mA VCC = MAX, VIN = 7.0 V 0.35 0.5 20 60 80 V A 2.7 3.5 0.25 0.4 V V 2.5 - 0.65 3.5 0.8 - 1.5 V V Min 2.0 0.7 V Typ Max Unit Ui V Test C di i T Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = - 18 mA , , VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V IIL IOS ICC mA mA mA VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V) Limits Symbol S bl fMAX tPLH tPHL Parameter P Maximum Clock Frequency Propagation Delay, pg y, Clock to Output Min 30 Typ 45 15 15 20 20 Max Unit Ui MHz ns ns VCC = 5.0 V 50 CL = 15 pF Test C di i T Conditions AC SETUP REQUIREMENTS (TA = 25C, VCC = 5.0 V) Limits Symbol S bl tW tW ts th Parameter P Clock Pulse Width Clear Pulse Width Setup Time Hold Time Min 20 25 20 0 Typ Max Unit Ui ns ns ns ns VCC = 5 0 V 5.0 Test C di i T Conditions FAST AND LS TTL DATA 5-2 |
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